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EDAptability offers EDA hard- and software which can easily be adapted to your existing work flows. Notice: EDAptability is seeking for an alpha customer for its latest DirectScan product. The tool targets ASIC production tests (stuck-at). We offer 10 times less test cycles than state-of-the-art methods. The test is capable of running at functional speed. The flow uses standard cells and achieves similar area results. Please contact us if you can think of an early engagement for this new technology. The latest products are:   Timing Driven RTL2RTL Partitioner                      - design partitioner tool for system prototyping       - enables super fast incremental synthesis       - enables physical synthesis       - full or semi automatic timing driven partitioning       - reads RTL (SystemVerilog, Verilog, VHDL)       - partitioning on RTL       - dumps RTL !!!       - supports switch-routing based systems                                                                   more ... RTL to Cycle-Accurate Model Converter                      - reads RTL (SystemVerilog, Verilog, VHDL)       - CA-model output in C or SystemC       - ultra fast execution algorithm                                                                   more ...   System - Prototyping - Emulator hardware SPE                     - uses latest Altera and/or Xilinx devices       - supports 1..10 devices, FPGA-wise extendable       - supports FPGAs with 1200 user-ios       - guaranteed best ever routing structure       - lowest system prototyping costs per FPGA       - switches or direct connectivity using plug-and-play       - 333MHz data rate connectivity btw. each FPGA (960ios)       - ALL FPGA io-pins directly accessible (no switch)       - bank voltage for ext. logic can be driven from ext.       - tightly coupled customer logic service       - integrated logic analyzer (2GB)       - SCEMI compatible                                                                   more ...   For further questions, feel free to watch the video or contact EDAptability. We are always glad to hear from you.

First professional fully or semi automated timing driven partitioner, partitioning
First true RTL System Prototyping software/tool.
State of the art RTL Prototyping, System Prototyping, Rapid Prototyping
State of the art RTL Partitioning, System Partitioning, Rapid Partitioning
next generation RTL partitioning technology, replacing edif netlist partitioning
Very easy to use for engineers with experience of Certify from Synplicity
Altera FPGA system partitioning, Xilinx FPGA system partitioning
reads .vb (Synplicity Verilog Board Description File),
reads .dvb (Dynamic Verilog Board Description File)
next generation RTL partitioner technology, replacing edif netlist partitioner
Altera FPGA system partitioner, Xilinx FPGA system partitioner
pin multiplexing is implemented on RTL level
XDR technology between FPGAs
Enables direct PCIe, DDR, QDR, XDR FPGA access in complex systems
Supports 960 and 1200 ios systems / system boards
RTL-to-RTL partitioner/partitioning supports Altera Spartan III, EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SL200, EP3SL260, EP2SL340, EP3SE50, EP3SE80, EP3SE110, EP3SE260
RTL-to-RTL partitioner/partitioning supports Altera Spartan II, EP2S15, EP2S30, EP2S60, EP2S90, EP2S130, EP2S180
RTL-to-RTL partitioner/partitioning supports Xilinx V5, XC5VLX30, XC5VLX50, XC5VLX85, XC5VLX100, XC5VLX220, XC5VLX330, , XC5VLX30T, XC5VLX50T, XC5VLX85T, XC5VLX110T, XC5VLX220T, XC5VLX330T, XC5VSX35T, XC5VSX50T, XC5VSX95T
RTL-to-RTL partitioner/partitioning supports Xilinx V4, XC4VLX15, XC4VLX25, XC4VLX40, XC4VLX60, XC4VLX80, XC4VLX100, XC4VLX160, XC4VLX200, XC4VLX15, XC4VSX25, XC4VSX35, XC4VSX55, XC4VFX12, XC4VFX20, XC4VFX40, XC4VFX60, XC4VFX100, XC4VFX140