EDAptability

Each FPGA-Board hosts one FPGA. The structure is compatible for FPGAs with less or equal 1200 user pins. The FPGA-Boards can be connected using switching or fixed routing boards.

FPGA-Boards of different FPGA providers Altera / Xilinx and different FPGA families can be mixed, so that each system can grow successively.

The following FPGAs are available. Further FPGA-Boards with specific Altera or Xilinx FPGAs can be offered based on customer request.

Altera	Xilinx
STRATIX IV E 530K 1760-FBGA	Virtex 5 XC5VLX330-2FFG1760C
STRATIX IV E 820K (please contact)	Virtex 6 (please contact)

The inner ring serves for the connectivity between two neighboring FPGA-Boards. They are normally not customer accessible. The FPGA-Boards are available in double-tube (guaranteed best possible switch routing with up to 4 FPGA-Boards) and triple-tube (guaranteed best possible switch routing with up to 6 FPGA-Boards).

The outer ring serves for application specific board (ASB) connectivity. That means, all IOs of the FPGA can be accessed. If an ASB is plugged in, the related bank voltage or Vref-pins can be driven/accessed from the ASB. The outer ring also serves as 5V and 3.3V power supply for the ASBs.

All 32 clocks of an FPGA can be accessed individual from outside through the SMB-sockets or from one of the 32 global clock sources. Each of the global clock sources can be driven from either the FPGA or from the related SMB-socket. 8 clock multiplexer with programmable factors of 4..40 and 32 clock divider with an programmable factor of 2..40 are available.

The board is powered through a 5V and 3.3V power supply. The FPGA-power supply is controlled by state of the art power regulators on board (PTH05000).

Each FPGA-Board has a programmed identification number, which can be readout by SPE-Control.

The fan on the bottom serves as cooling-fan for the FPGA on the board below.