EDAptability

Cycle Accurate C/SystemC Model Generator

This tool generates cycle accurate C or SystemC models of the design. The (cycle or timing accurate) models are plain text and can be used in other C- or SystemC environment, they are ANSI-C compliant and can be compiled with any C-compiler. No additional library is needed. The compiled code enables a license free ultra fast execution.

During execution, the C-code of the design can generate a VCD-file, if signals are selected previously. The integrated VCD-Viewer or any other third party tool can be used to look at these signals.

The Model Generator supports SystemVerilog (including SVAs), Verilog, VHDL and PSL.

Please contact us, if you have any further questions regarding the product. We are always happy to hear from you.