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The
CoreMultiplier reads
RTL (VHDL, Verilog, SystemVerilog) and
dumps the modified RTL source code in original format after a GUI or
script based definition process. The output can/must be used as source
for the verification process and synthesis.
Each
hyper pipelined design has less area than the sum of its individual
implementations on the ASIC/FPGA. This is the main benefit. By
multiplying the clock frequency, the performance of the design is the
same as the sum of the individual implementations. It is important to
notice, that each "new" core works totally independent of the others.
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Examples
are:
- processors (ARM, MIPS,
...),
- DSPs (filters,
...),
- peripherals
(Ethernet, DMA,
...),
- bus-systems
(AMBA, OCPIP, ...) or
- complete
subsystems of a design.
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For
memory-less designs, the customer cases indicate,
that you get 4 cores for the design size of 2 in an ASIC technology.
The benefit on an FPGA is even more dramatic, since the registers
already exists. In this case, the utilization rises and the number of
occupied slices rises only slightly.
Each
applications has additional features. Processors can
share one physical D-cache or part of register-files eliminating the
need of transferring data over a system-bus. DSPs can work at full
processing speed, eliminating the need of storing data in memory first
and generating no system latency.
Bus-systems and DMAs can multiply their bandwidth, although single
cycle
read/write requests exists.
Examples with detailed
documentation and source code can be found at OpenCores:
Hyper Pipelined Open RISC OR1200 Core,
http://opencores.com/project,or1200_hp, (Verilog)
Hyper Pipelined AVR Core,
http://opencores.com/project,avr_hp, (VHDL)
Customer
cases also indicate, that the production test of
a hyper-pipelined core is extremely faster than CMF individual cores
due
to the less complex logic cones, saving not only die size but also
tester time. One customer uses non-scan registers as pipe-registers,
which results in the same test time for the hyper-pipelined cores as
for one single core but even reduces the size of the hyper-pipelined
core any further.
EDAptability’s
SynEDA Core Multiplier
supports Solaris, Windows and Linux.
Please contact us,
if you have any further questions regarding the
product. We are always happy to hear from you.
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