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From the user perspective it looks like a
simulator. Signal selection can be done on RTL
level, the "simulation" might need to be rerun
again and the signals are displayed. Then
other signals and time-zones of interests are
selected and the process is repeated until the
bug is found. The difference here is, that the
"simulation" runs on the ASIC, FPGA
stand-alone or FPGA based system prototyping
system (running at for example 80 MHz) and
true register behaviors are traced.
It is
important to notice, that no re-synthesis needs to be done during
the debugging process or due to debugging related issues at all.
All
RTL-signals can be displayed, including registers, memory-content
and non register signals (combinatorial signals). Also the type of
the signals remains as defined (enumeration, arrays, records,
...). The signals are dumped in a VCD-file, which can be accessed
by EDAptability's VCD viewer or any third party VCD viewer.
The clocks don't need
to be controlled. The system can run freely and continuously and
clocks can be driven from external as well. The postsimulation
starts shortly before the user selected timeframe. The time
between the start and the selected timeframe don't need to be
simulated.
There is no direct
impact on the timing behavior of the design and only a minor
impact on the area.
EDAptability’s SynEDA TotalScope feature supports Solaris, Windows and Linux.
Please
contact us, if you have any further questions regarding the
product. We are always happy to hear from you.
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