Only four major advantages are mentioned here:

1) The user can run simulations/regressions on the partitioned design to make sure that partitioning hasn’t introduced errors (debugging on board level can be very time consuming) and that additional RTL resources (wrappers, ...) work fine within the partitioned code. The original testbench can be reused, since the hierarchy remains the same, only one FPGA-level is introduced on top.

2) The second main advantage is that the synthesis can be done for each FPGA stand alone. This gives better synthesis results and incremental RTL changes can be handled much faster (due to continuously improving incremental flows of FPGA-providers).

3) The high-level database enables an ultra-fast STA, also considering feedthroughs and pin-multiplexing timing. Due to this fact, the integrated STA-engine can guide the user and the auto-placer/router in order to truly reach the fastest possible partitioning result to fully utilize expensive speed optimized hardware.

4) The overall project becomes less critical, since the partitioning-tool is mostly used at the beginning of the project, also working on a small but sufficient database. At the critical phase at the end of the project, only incremental synthesis tools are used.

The design is elaborated to estimate the design resources. Constant signals are propagated and clock domains are detected. After that a high-level database is created and all irrelevant information is removed. This enables a fast GUI interactivity and memory size problems are not an issue. The user can also read in edif- and/or vqm netlists of subdesigns for analyses. If not provided, the partitioner estimates the logic elements and detects register and memory sizes even for very large designs within seconds. The user also has the possibility to manually define these resource attributes for subdesigns.

After flattening the design to a user defined level (block-wise), it can be placed fully manual into the FPGA or black boxes (external memories, connectors, …). The tool has an integrated fully-automated placer. It calculates all possible place solutions and proposes the 10 fastest one (corner cases). The fully-automated placer algorithm can also start after initial manual placing. The user can go to any step of the auto-placer progress and continue from there with user specific placement (the auto-placer can continue again as long as elements are not placed).

The router algorithm also routes the design automatically (timing driven) or the user can define the routing by hand. Also a mixture of both approaches is possible.

If you have switch routing capabilities on your hardware system, the dynamic board description file is read and the routing algorithm sets these switches to reach the best possible routing solution.

If pin multiplexing is enabled, the tool automatically introduces (timing-driven) pin multiplexing RTL logic, including features like noise reducing logic, NDR-technology and/or LVDS based FPGA to FPGA connections.

The integrated timing engine detects the clock domains and gives the user at any point of time during the partitioning process the system overall static timing analyses for each defined clock domain timing.

The unique placer GUI gives the user a complete overview of the key data the user needs to make further decisions. It shows for example the unplaced design elements, the remaining/used FPGA and routing resources and the recent STA results.

Most projects use RTL sources that are optimized for the ASIC flow. Besides partitioning tasks, system prototyping engineers also need to do FPGA based modifications on the ASIC-RTL (introducing clock management modules, connect, reconnect, tie signals, …). This can be done via a Tcl-interface.

The partitioner supports Actel, Altera, Xilinx and other user defined FPGAs. A mixture of different FPGA types is possible. EDAptability and some other board manufactures use switch elements to optimize the board level routing. These switches are detected and dynamically set/unset during the place and route process. This results in a great flow simplification and saves the user a lot of time to find the best board level routing solution.

The well known undo/redo/goto functionality allows the user to explore different manual, semi-auto or auto place and route solutions easily. E.g.: any auto-partitioning result can be undone to a user selected step, a different command is inserted and the auto-partitioning tool starts again from there.

EDAptability’s SynEDA partitioner supports Solaris, Windows and Linux.

Please contact us, if you have any further questions regarding the product. We are always happy to hear from you.