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EDAptability launches SynEDA Mixed Language Simulator and RTL to C Model Transformer released MUNICH, Germany, January 15, 2004 - EDAptability today announced its new tool SynEDA. The current version includes a mixed language (Verilog, VHDL) simulator HS and an RTL to C Model Transformer CG. The tool combines synthesis algorithms with simulation techniques. This approach makes the RTL simulation behave like the high level functional design representation after synthesis. The technology benefit comes from a central cycle accurate C model of the design, which can deliver the fastest possible runtime as a compiled executable, as well as from the fact, that hardware and software developer can share the same C model, which itself is a the high level functional design representation after synthesis.
EDAptability's
SynEDA
includes the mixed language simulator HS and the RTL to C Model
Transformer CG.
EDAptability provides leading edge EDA tools for the complete ASIC and FPGA market. EDAptability's mixed language simulator and EDAptability's RTL to C Model Transformer enable the customer to close the Hardware-Software-Co-Development gap. Its state of the art technology enables the user to run the fastest possible simulation and shortens simulation and verification time significantly. For more information, visit www.EDAptability.com.
For more information contact: Tobias Strauch
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