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EDAptability enables simulation over the www Simulator with IP-access over the www released MUNICH, Germany, September, 10th, 2005 - EDAptability today announced that it extended its simulator by an infrastructure generator, that enables simulation over the www. The simulator is based on a transformer, that converts RTL source code into cycle accurate C-Models and converts testbenches into timing accurate C++-Models. If both kind of models are linked and compiled the design can be simulated. The IP-provider (or any design team) can compile the cycle accurate C-Model to an CGI file which is placed on the server. The chip-designer can now access this design buy defining the URL. If the compiled models are executed, the execution accesses the IP-provider model on the server. The
IP-provider can
enable the feature, that a VCD-file is dumped while accessed. This
gives him the possibility to debug the customer testcase. The user can
explore different design behaviors without having received the IP
previously.
EDAptability's SynEDA
2.1 includes the mixed language simulator HS and the RTL to C/Java
Model Transformer CG/JG.
EDAptability provides leading edge EDA tools for the complete ASIC and FPGA market. EDAptability's mixed language simulator and EDAptability's testbench/design to timing/cycle accurate C/Java Model Transformer enable the customer to close the Hardware-Software-Co-Development gap. Its state of the art technology enables the C-user to run the fastest possible simulation and shortens simulation and verification time significantly. For more information, visit www.EDAptability.com.
For more information contact: Tobias Strauch
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