EDAptability offers EDA hard- and software which can easily be adapted
to your existing work flows. The SynEDA environment has the following
key components. Each component can work stand alone:
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CoreMultiplier
- multiplies
functionality of cores,
bus-systems and
complete
subdesigns with
reduces
area
- reads RTL
(SystemVerilog, Verilog, VHDL)
- dumps RTL
!!!
- works for FPGA and ASIC technology
more ...
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System-Prototyping-Emulator
hardware SPE Gen2
-
uses
latest Altera and/or Xilinx devices
- supports
1..7 devices, FPGA-wise extendable
- new:
PCIe Gen2 x8 connection to each FPGA board
- new:
two 4GB DDR3 SDRAMs on each FPGA board
- supports FPGAs
with 1200 user-ios
-
guaranteed best ever routing structure
-
108MHz
w.c. system-performance (reg. to reg.)
- 333MHz
wave pipelining btw. all FPGA IOs
- 1/4
of FPGA IOs directly
accessible (no switch)
- bank
voltage for ext. logic can be driven from ext.
- SCEMI compatible
more ...
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RTL - to - RTL Partitioner
-
reads
RTL (VHDL, Verilog,
SystemVerilog)
- dumps
modified RTL source
code in original format
- GUI or
script based
partitioning
- semi
and/or full
automated partitioning
- integrated board-switch setting feature
-
STA
capabilities for
timing driven partitioning
more ...
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RTL to
Cycle-Accurate Model Converter
- reads RTL
(SystemVerilog, Verilog,
VHDL)
- CA-model
output in C or SystemC
- ultra fast
execution algorithm
- supports SVAs and
PSL
more ...
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Please contact us, if you have any further questions regarding the
product. We are always happy to hear from you.
Notice:
EDAptability is seeking for an alpha customer for its latest DirectScan
product. The tool targets ASIC production tests (stuck-at). We offer 10
times less test cycles than state-of-the-art methods. The test is
capable of running at functional speed. The flow uses standard cells
and achieves similar area results. Please contact us if you can think
of an early engagement for this new technology.
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