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System-Prototyping-Emulator hardware
SPE
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uses latest
Altera and/or Xilinx devices
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supports
1..10 devices, FPGA-wise extendable
- supports FPGAs with 1200 user-ios
- guaranteed best
ever
routing structure
- lowest system prototyping costs per FPGA
- switches or direct connectivity using
plug-and-play
-
333MHz
data rate
connectivity
btw. each FPGA
(960ios)
- ALL FPGA io-pins
directly accessible (no switch)
- bank voltage for ext. logic can be driven
from ext.
- tightly coupled customer
logic service
- integrated logic analyzer (2GB)
- SCEMI compatible
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RTL - to - RTL partitioner
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reads RTL
(VHDL, Verilog, SystemVerilog)
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dumps
modified RTL source code in original format
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GUI or
script based partitioning
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semi and/or
full automated partitioning
- integrated board-switch setting feature
-
STA
capabilities for timing driven partitioning
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RTL to Cycle-Accurate Model Converter
- reads RTL
(SystemVerilog, Verilog, VHDL)
- CA-model output in C or SystemC
- ultra fast execution algorithm
- supports SVAs and PSL
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Transaction Generator
(early access only)
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graphical entry tool for transaction behavior
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optional SCE-MI interface generator
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synthesize-able transaction code generator
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push-button scenario
view
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