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FPGA/ASIC Debugging environment
TotalScope
-
RTL level
signal selection
- 100 %
signal visibility
- no resynthesis
needed
- no timing impact
- only minor area
impact
- no slow-down at runtime (freely running clocks)
- optional data streamer and cable hardware
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System-Prototyping-Emulator hardware
SPE
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uses latest
Altera and/or Xilinx devices
-
supports
1..10 devices, FPGA-wise extendable
- supports FPGAs with 1200 user-ios
- guaranteed best
ever
routing structure
- lowest system prototyping costs per FPGA
- switches or direct connectivity using
plug-and-play
-
333MHz DDR
based con. btw. each FPGA (960ios)
- ALL FPGA io-pins
directly accessible (no switch)
- bank voltage for ext. logic can be driven
from ext.
- tightly coupled customer
logic service
- integrated logic analyzer (2GB)
- SCEMI compatible
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RTL - to - RTL partitioner
-
reads RTL
(VHDL, Verilog, SystemVerilog)
-
dumps
modified RTL source code in original format
-
GUI or
script based partitioning
-
semi and/or
full automated partitioning
- integrated board-switch setting feature
-
STA
capabilities for timing driven partitioning
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Simulator and Cycle
C++/SystemC Model Generator
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supports VHDL, Verilog, ANSI-C and SystemC
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generates cycle accurate C or SystemC models of
the
design
-
generates timing accurate C++ or SystemC models
of the
testbench
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generates .exe for license free ultra fast execution
- state-of-the-art VCD Viewer
-
regression runner
- supports simulation over the
www
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Transaction Generator
(early access only)
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graphical entry tool for transaction behavior
-
optional SCE-MI interface generator
-
synthesize-able transaction code generator
-
push-button scenario
view
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