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CoreMultiplier
- multiplies
functionality of cores,
bus-systems and
complete
subdesigns with
reduces
area
- reads RTL
(SystemVerilog, Verilog, VHDL)
- dumps RTL
!!!
- works for FPGA and ASIC technology
more ...
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RTL - to - RTL Partitioner
-
reads
RTL (VHDL, Verilog, SystemVerilog)
- dumps
modified RTL source code in original format
- GUI or
script based partitioning
- semi
and/or full automated partitioning
- integrated board-switch setting feature
-
STA
capabilities for timing driven partitioning
more ...
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RTL to
Cycle-Accurate Model
Converter
- reads RTL
(SystemVerilog, Verilog, VHDL)
- CA-model
output in C or SystemC
- ultra fast
execution
- supports SVAs and
PSL
more
...
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Please contact us, if you have any further questions regarding the
product. We are always happy to hear from you.
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