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RTL - to - RTL partitioner
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reads RTL
(VHDL, Verilog, SystemVerilog)
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dumps
modified RTL source code in original format
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GUI or
script based partitioning
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semi and/or
full automated partitioning
- integrated board-switch setting feature
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STA
capabilities for timing driven partitioning
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RTL to Cycle-Accurate Model Converter
- reads RTL
(SystemVerilog, Verilog, VHDL)
- CA-model output in C or SystemC
- ultra fast execution
- supports SVAs and PSL
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Transaction Generator
(early access only)
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graphical entry tool for transaction behavior
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optional SCE-MI interface generator
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synthesize-able transaction code generator
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push-button scenario
view
more ...
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Please
contact us, if you have any further questions regarding the
product. We are always happy to hear from you.
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