The Complete SPE-Systems can host FPGA-Boards with up to 1200 user pins. FPGA-Boards of different FPGA providers Altera / Xilinx and different FPGA families Virtex4 / Virtex5 can be mixed, so that each system can grow successively.

Each pre-assembled system has one Base-Board and 1..6 FPGA-Boards respectively. The Base-Board serves as configuration control board (Base-Board-C). It can additionally host the integrated logic analyzer. It is then called Base-Board-LA and can be extended with up to 2GB DDR2 SDRAM to store the VCD-file.

The Base-Board stores the configuration data for the FPGAs on the FPGA-Boards as well as the switch routing configuration. The configuration is downloaded via USB. A PCI interface is under development.

In between the FPGA-Boards Switch-Routing-Boards are placed. They connect the various IOs of the FPGAs. By default the systems are pre-assembled with Switch-Routing-Boards to guarantee the best ever routing structure. Alternatively Fixed-Routing-Boards can be used instead.
 

Due to the short distance between the FPGAs, between the switches and between FPGAs and switches, it is also the fastest possible routing structure. This switch routing structure is qualified for 333 MHz DDR based connectivity over 1200 signals. The worst case system frequency (register-to-register) in a 4 Altera FPGA based system is 210 MHz (1200 ios switching at the same time/clock-edge).

The system has 32 global clock resources. The clock management devices on each FPGA-Board guarantee a global clock skew below 100 ps. Each global clock resource can be driven from any FPGA, from an external clock source or it can be driven by one of the multipliers (factor 4...40) or dividers (divider 2...40) in one of the clock management devices on each FPGA-Board. These multipliers/dividers again can be driven by any FPGA, global clock source or external clock source. The insertion delay of external clocks can be modified.
 

A license free software SPE-Control, running an all operating systems handles the switch setting mechanism and controls the download of configuration data via an USB interface. It generates a system Verilog file to be used in third party partitioning tools. EDAptability's partitioner has an integrated switch setting optimizer. This switch setting definition can be read with SPE-Control.

The integrated logic analyzer is also controlled by the license free software SPE-Control. Trigger-states can be defined and downloaded. The resulting VCD-file is uploaded and can be viewed with the integrated VCD viewer or any other third party VCD viewer.

The cooling of the system is managed by the Base-Board. 2 fans create an air-in-flow and 2 fans create the air-out-flow. This air flow then runs through the complete system. Each FPGA-Board carries one additional fan which creates a flow from the air-flow to the air-out flow directly through the cooling bodies of the FPGAs. The temperature measurement of each FPGA guarantees the optimal air flow. Due to the high quality fans and the minimum power needed because of the optimal flow, the system is very silent.

The casing is a very flexible alu-box, which can be extended with each additional FPGA-Board. The stripes on each side can be removed and replaced by ASB-holder strips.

The complete system is SCEMI compatible.

The complete system is delivered with an external power supply device, which can handle the complete 90V-250V range.

For further questions, feel free to watch the video or contact EDAptability. We are always glad to hear from you.