The resulting behavior can be dumped as synthesizeable VHDL or Verilog code.

A free set of AHB and whishbone transactions are provided. The user can easily generate a synthesizable testbench, which talks on one side with the user design ios (USB, PCI, ...) and on the other side with another customer defined interface. Alternatively it can easily be connected as master or slave with an internal system AHB bus, or with an additional debug wishbone bus. The design and the generated code can then be synthesized for FPGAs and the design can then be transaction based "self-stimulated".

The transaction code can also be dumped as SCEMI compliant.

If EDAptability's simulator is purchased, the transaction code and the IP-code is simulated (push-button) and the behavior can be seen with the integrated VCD-viewer and the transaction messages can be seen. Otherwise any other simulator can be used.

If you are interested in using this technology as an early access customer, please contact EDAptability.